1. Field of the Invention
The present invention relates to a data transmission controller and decoder and a data transmission method thereof, and more particularly to a serial transmission controller and decoder and a serial transmission method thereof.
2. Description of Related Art
Conventionally, the access interface of memory device such as the flash memory uses an address and data bus having a parallel transmission interface. However, this type of interface requires a large number of leads and a higher chip packaging cost. Therefore, to reduce the number of leads, a serial transmission interface, for example, a serial peripheral interface (SPI) is widely adopted.
FIG. 1 is a diagram showing the data transmission pathways of a conventional serial peripheral interface. As shown in FIG. 1, the main control terminal 150 and the SPI flash memory 100 (the controlled terminal) transmit information to each other through the serial transmission interface. The serial transmission interface includes the SPI controller 160 of the main control terminal 150 and the SPI controller 110 of the SPI flash memory. The SPI controller 160 and the SPI controller 110 communicate with each other through the serial clock signal SCK, the enable signal CE_B and the external data. The SPI controller 110 and the flash memory 120 inside the SPI flash memory 100 communicate with each other through the address data, the internal data, the enable signal CE_B, the write-enable signal WE_B and the read-enable signal OE_B.
FIG. 2 is a clock diagram of the data transmission in FIG. 1. The SPI interface in FIG. 1 uses four leads (that is, the DI, DO, SCK and CE leads) to carry out synchronous serial communication. The CE lead transmits the enable signal CE-B. The DI and DO leads are used to transmit data into and out of the flash memory respectively. The SCK lead is used to transmit a clock signal so as to synchronize the data transmission of the flash memory. In the rising edge of the serial clock signal (SCK), data is latched into the flash memory. In the falling edge of the serial clock signal (SCK), data is transmitted from the flash memory. Because the data is transmitted in serially, the flash memory with this SPI interface needs fewer leads.
However, the current serial transmission interface (SPI) uses a fixed field length to transmit different control commands and address information. Moreover, different control commands are used to transmit related data bits. Thus, if the data read-out addresses are discontinuous, command and address bits must be re-submitted. Hence, the transmission efficiency is low so that the conventional SPI can hardly provide the bandwidth requirement of current high-speed systems.